An activity monitor for power/performance tuning of CMOS digital circuits
In: Integrated circuit and system design (power and timing modeling, optimization and simulation)Lecture notes in computer science; (2005) S. 187-196
Konferenz
- print, 9 ref
Zugriff:
The requirement to control each possible degree of freedom of digital circuits becomes a necessity in deep submicron technologies. This requires getting a set of monitors to measure each one of the parameters of interest. This paper describes a monitor fabricated in a 90nm CMOS technology which is able to estimate the circuit activity. The output of such monitor can be used as a tool to decide how to adjust the circuit working conditions to get the best power/performance circuit response. The paper presents the implementation and experimental results of a test chip including such monitor.
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An activity monitor for power/performance tuning of CMOS digital circuits
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Autor/in / Beteiligte Person: | RIUS, Josep ; PINEDA, José ; MEIJER, Maurice |
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Quelle: | Integrated circuit and system design (power and timing modeling, optimization and simulation)Lecture notes in computer science; (2005) S. 187-196 |
Veröffentlichung: | Berlin: Springer, 2005 |
Medientyp: | Konferenz |
Umfang: | print, 9 ref |
ISSN: | 0302-9743 (print) |
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