Compact static power model of complex CMOS gates
In: Integrated circuit and system design (power and timing modeling, optimization and simulation)Lecture notes in computer science; (2005) S. 348-354
Konferenz
- print, 5 ref
Zugriff:
We present a compact model to estimate quickly and accurately the leakage power in CMOS nanometer Integrated Circuits (ICs). The model has similar accuracy than SPICE and represents an important improvement with respect to previous works. It has been developed to be used for fast and accurate estimation and optimization of the standby power dissipated by large circuits.
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Compact static power model of complex CMOS gates
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Autor/in / Beteiligte Person: | ROSSELLO, Jose L ; BOTA, Sebastia ; SEGURA, Jaume |
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Quelle: | Integrated circuit and system design (power and timing modeling, optimization and simulation)Lecture notes in computer science; (2005) S. 348-354 |
Veröffentlichung: | Berlin: Springer, 2005 |
Medientyp: | Konferenz |
Umfang: | print, 5 ref |
ISSN: | 0302-9743 (print) |
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