A cost-efficient 0.18μm CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications
In: Proceedings of the IEEE 2004 custom integrated circuits conference (Orlando, Florida, October 3-6, 2004) :405-408
Konferenz
- print, 6 ref 1
Zugriff:
A single-chip 2.4GHz, zero-IF transceiver for IEEE 802.11b/g WLAN systems is fabricated on a 0.18pm CMOS technology. Based on an innovative system architecture using digital calibration, analog circuit imperfections are eliminated. The transceiver features enhanced phase noise performance with the use of a Fractional-N synthesizer. A switched configuration allows for the same filters to be used on both TX/RX paths, thus minimizing area. It features a NF of 3.5dB While the sensitivity is -78dBm at 54Mb/s operation, referred at the input of the chip. The transmit output 1dB compression point is 9dBm. Digital calibration helps achieve an EVM of -31dB while transmitting -4dBm at 54 Mb/s.
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A cost-efficient 0.18μm CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications
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Autor/in / Beteiligte Person: | HARALABIDIS, N ; VAVELIDIS, K ; MERAKOS, P ; BOURAS, I ; BOURAS, S ; PLEVRIDIS, S ; VASSILIOU, I ; GEORGANTAS, T ; YAMANAKA, A ; KAVADIAS, S ; KAMOULAKOS, G ; KAPNISTIS, C ; KOKOLAKIS, Y ; KYRANAS, A |
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Quelle: | Proceedings of the IEEE 2004 custom integrated circuits conference (Orlando, Florida, October 3-6, 2004) :405-408 |
Veröffentlichung: | Piscataway NJ: Institute of Electrical and Electronics Engineers, 2004 |
Medientyp: | Konferenz |
Umfang: | print, 6 ref 1 |
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