An integrated 0.35 μm CMOS optical receiver with clock and data recovery circuit
In: Microelectronics journal, Jg. 37 (2006), Heft 9, S. 985-992
academicJournal
- print, 19 ref
Zugriff:
This paper presents an integrated optical receiver that operates at 1 Gb/s in a standard 0.35 μm digital CMOS technology. The receiver consists of an integrated CMOS photodetector, a transimpedance amplifier (TIA) followed by a post-amplification stage and a dual-loop clock and data recovery (CDR) circuit. At a wavelength of 860 nm, the circuit requires an average light input power of -19.7dBm to obtain a bit-error rate (BER) of 10-12. The complete receiver consumes a total power of approximately 155mW from a 3.3-V supply. The core circuit area is 0.85 × 1.32 mm2.
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An integrated 0.35 μm CMOS optical receiver with clock and data recovery circuit
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Autor/in / Beteiligte Person: | CHEN, Yi-Ju ; DU PLESSIS, Monuko |
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Zeitschrift: | Microelectronics journal, Jg. 37 (2006), Heft 9, S. 985-992 |
Veröffentlichung: | Oxford: Elsevier Science, 2006 |
Medientyp: | academicJournal |
Umfang: | print, 19 ref |
ISSN: | 0959-8324 (print) |
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