A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking
In: 2005 Custom Integrated Circuits ConferenceIEEE journal of solid-state circuits 41(8):1894-1907; Jg. 41 (2006) 8, S. 1894-1907
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Zugriff:
This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inyersion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance.
Titel: |
A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking
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Autor/in / Beteiligte Person: | LOKE, Alvin L. S ; BARNES, Robert K ; TIN TIN, WEE ; OSHIMA, Michael M ; MOORE, Charles E ; KENNEDY, Ronald R ; GILSDORF, Michael J |
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Quelle: | 2005 Custom Integrated Circuits ConferenceIEEE journal of solid-state circuits 41(8):1894-1907; Jg. 41 (2006) 8, S. 1894-1907 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2006 |
Medientyp: | Konferenz |
Umfang: | print, 33 ref |
ISSN: | 0018-9200 (print) |
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