Design of an improved CMOS phase/frequency detector
In: Circuits, systems, and signal processing, Jg. 25 (2006), Heft 4, S. 539-557
Online
academicJournal
- print, 11 ref
Zugriff:
A complementary metal oxide semiconductor (CMOS) phase/frequency detector (PFD) is presented. An improved CMOS D-type master-slave flip-flop is described and adopted in the PFD. Higher speed and lower power operation is attributed to the reduced node capacitance. Charge-sharing phenomena are circumvented in the proposed flip-flop and PFD. The maximum frequency of operation of the PFD is analytically studied. Device-sizing equations, based upon a first-order approximation, for the PFD are derived. The proposed PFD shows improvements in both phase and frequency sensitivities at high operating frequencies. HSPICE simulations of a phase-locked loop (PLL) employing the improved PFD demonstrate a faster frequency acquisition. The PLL simulations also verify that the maximum operating frequency of the PFD is in agreement with our analytical results.
Titel: |
Design of an improved CMOS phase/frequency detector
|
---|---|
Autor/in / Beteiligte Person: | CHEN, Roger Yubtzuan ; HUANG, Hong-Yu ; HSIEH, Ming-Yu |
Link: | |
Zeitschrift: | Circuits, systems, and signal processing, Jg. 25 (2006), Heft 4, S. 539-557 |
Veröffentlichung: | Heidelberg: Springer, 2006 |
Medientyp: | academicJournal |
Umfang: | print, 11 ref |
ISSN: | 0278-081X (print) |
Schlagwort: |
|
Sonstiges: |
|