Integrating ENSEMBLE™ PMD low-k at the PMD level of CMOS logic circuits
In: Microelectronic engineering 83(11-12):2303-2308; Jg. 83 (2006) 11-12, S. 2303-2308
Konferenz
- print, 2 ref
Zugriff:
In this paper, we report on the integration of a spin-on low-k material (ENSEMBLE™ PMD) at the pre-metal dielectric (PMD) level of CMOS logic circuits processed using 0.13 μm node modules. Modifications to the conventional integration flow, where high-density plasma phospho-silicate glass (HDP-PSG) is used as PMD material, are made to the planarization steps and etch/strip sequence. Although on stand-alone transistors there is no measurable impact of the lower capacitance, a significant decrease of the switching delay of invertors in ring oscillator structures loaded with a metal/poly plate capacitor is observed. This demonstrates the possible positive impact of low-k on the performance of circuits of which the lowest level of back-end routing has a large overlap to underlying silicided areas.
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Integrating ENSEMBLE™ PMD low-k at the PMD level of CMOS logic circuits
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Autor/in / Beteiligte Person: | DEMUYNCK, S ; DE MARNEFFE, J. F ; MILLS, L ; LE, Q. T ; VOS, I ; DEVRIENDT, K ; VAN HOVE, M ; WAETERLOOS, J ; HOWARD, K ; POPA, P ; WILSON, L |
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Quelle: | Microelectronic engineering 83(11-12):2303-2308; Jg. 83 (2006) 11-12, S. 2303-2308 |
Veröffentlichung: | Amsterdam: Elsevier Science, 2006 |
Medientyp: | Konferenz |
Umfang: | print, 2 ref |
ISSN: | 0167-9317 (print) |
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