A +31.5 dBm CMOS RF doherty power amplifier for wireless communications
In: 2006 IEEE International Solid-State Circuits ConferenceIEEE journal of solid-state circuits 41(12):2852-2859
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Zugriff:
A fully differential Doherty power amplifier (PA) is implemented in a 0.13-μm CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25 dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky A/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8 x 3.2 mm2 including all pads and bypass capacitors.
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A +31.5 dBm CMOS RF doherty power amplifier for wireless communications
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Autor/in / Beteiligte Person: | WONGKOMET, Naratip ; TEE, Luns ; GRAY, Paul R |
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Quelle: | 2006 IEEE International Solid-State Circuits ConferenceIEEE journal of solid-state circuits 41(12):2852-2859 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2006 |
Medientyp: | Konferenz |
Umfang: | print, 15 ref |
ISSN: | 0018-9200 (print) |
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