Low-voltage topologies for 40-Gb/s circuits in nanoscale CMOS
In: ESSCIRC 2006IEEE journal of solid-state circuits 42(7):1564-1573; Jg. 42 (2007) 7, S. 1564-1573
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Zugriff:
This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-VT MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design.
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Low-voltage topologies for 40-Gb/s circuits in nanoscale CMOS
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Autor/in / Beteiligte Person: | CHALVATZIS, Theodoros ; YAU, Kenneth H. K ; AROCA, Ricardo A ; SCHVAN, Peter ; YANG, Ming-Ta ; VOINIGESCU, Sorin P |
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Quelle: | ESSCIRC 2006IEEE journal of solid-state circuits 42(7):1564-1573; Jg. 42 (2007) 7, S. 1564-1573 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2007 |
Medientyp: | Konferenz |
Umfang: | print, 21 ref |
ISSN: | 0018-9200 (print) |
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