CMOS inverter based on gate-all-around Silicon-Nanowire MOSFETs fabricated using Top-Down approach
In: IEEE electron device letters, Jg. 28 (2007), Heft 11, S. 1021-1024
Online
academicJournal
- print, 21 ref
Zugriff:
-This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achieve symmetric pull-up and pull-down, sharp ON-OFF transitions with high voltage gains (e.g., ΔVOUT /A V IN up to ∼40 for VDD = 1.2 V) are obtained. The inverter maintains its good transfer characteristics and noise margins for wide range of VDD tested down to 0.4 V. Individual transistors show excellent subthreshold characteristics and drive currents. The results are discussed in light of the circuit performances reported for other advanced nonclassical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS-circuit functionality is thus demonstrated.
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CMOS inverter based on gate-all-around Silicon-Nanowire MOSFETs fabricated using Top-Down approach
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Autor/in / Beteiligte Person: | RUSTAGI, S. C ; SINGH, N ; FANG, W. W ; BUDDHARAJU, K. D ; OMAMPULIYUR, S. R ; TEO, S. H. G ; TUNG, C. H ; LO, G. Q ; BALASUBRAMANIAN, N ; KWONG, D. L |
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Zeitschrift: | IEEE electron device letters, Jg. 28 (2007), Heft 11, S. 1021-1024 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2007 |
Medientyp: | academicJournal |
Umfang: | print, 21 ref |
ISSN: | 0741-3106 (print) |
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