Tensile-strained germanium CMOS integration on silicon
In: IEEE electron device letters, Jg. 28 (2007), Heft 12, S. 1117-1119
Online
academicJournal
- print, 16 ref
Zugriff:
-Monolithic integration of tensile-strained Si/ Germanium (Ge)-channel n-MOS and tensile-strained Ge p-MOS with ultrathin (equivalent oxide thickness ∼14Å) HfO2 gate dielectric and TaN gate stack on Si substrate is demonstrated. Defect-free Ge layer (279 nm) grown by ultrahigh vacuum chemical-vapor deposition is achieved using a two-step Ge-growth technique coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ∼0.67% and exhibits a peak hole mobility of 250 cm2 /V. s which is 100% higher than the universal Si hole mobility. The gate leakage current is two orders of magnitude lower compared to the reported results on Ge bulk.
Titel: |
Tensile-strained germanium CMOS integration on silicon
|
---|---|
Autor/in / Beteiligte Person: | ZANG, H ; LOH, W. Y ; YE, J. D ; LO, G. Q ; BYUNG JIN, CHO |
Link: | |
Zeitschrift: | IEEE electron device letters, Jg. 28 (2007), Heft 12, S. 1117-1119 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2007 |
Medientyp: | academicJournal |
Umfang: | print, 16 ref |
ISSN: | 0741-3106 (print) |
Schlagwort: |
|
Sonstiges: |
|