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In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 μs/5 ms) and low programming current (3.5 μA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

Titel:	Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory
Autor/in / Beteiligte Person:	WU, Woei-Cherng ; CHAO, Tien-Sheng ; JHYY CHENG, LIOU ; TZU PING, CHEN ; CHIEN HUNG, CHEN ; CHIH HUNG, LIN ; HWI HUANG, CHEN ; KO, Joe ; PENG, Wu-Chin ; YANG, Wen-Luh ; CHEN, Jian-Hao ; MING WEN, MA ; LAI, Chao-Sung ; YANG, Tsung-Yu ; LEE, Chien-Hsing ; HSIEH, Tsung-Min
Link:	Full Text Finder (Volltext) E-Journal im Bestand der UB Hagen? View record from PASCAL Archive
Zeitschrift:	Semiconductor science and technology, Jg. 23 (2008), Heft 1
Veröffentlichung:	Bristol: Institute of Physics, 2008
Medientyp:	academicJournal
Umfang:	print, 32 ref
ISSN:	0268-1242 (print)
Schlagwort:	Electronics Electronique Optics Optique Condensed state physics Physique de l'état condensé Sciences exactes et technologie Exact sciences and technology Sciences appliquees Applied sciences Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Circuits intégrés Integrated circuits Conception. Technologies. Analyse fonctionnement. Essais Design. Technologies. Operation analysis. Testing Circuits intégrés par fonction (dont mémoires et processeurs) Integrated circuits by function (including memories and processors) Stockage et lecture de l'information Storage and reproduction of information Mémoires de masse magnétiques et optiques Magnetic and optical mass memories Circuit intégré Integrated circuit Circuito integrado Dispositif à mémoire Memory devices Effacement Erasure Borradura Evaluation performance Performance evaluation Evaluación prestación Grille transistor Transistor gate Rejilla transistor Mémoire non volatile Non volatile memory Memoria no volátil Optimisation Optimization Optimización Oxyde grille Gate oxide Oxido rejilla Structure SONOS SONOS structure Estructura SONOS Système n niveaux Multilevel system Sistema n niveles
Sonstiges:	Nachgewiesen in: PASCAL Archive Sprachen: English Original Material: INIST-CNRS Document Type: Article File Description: text Language: English Author Affiliations: Department of Electrophysics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Tawain, Province of China ; Solid State System Corp., Tai Yuen Hi-Tech Industrial Park, 5F-1, No. 22, Tai Yuen Street, Jubei City, Hsinchu, Tawain, Province of China ; United Microelectronics Corporation (UMC), Special Technology Division, No. 3, Li-Hsin Road II, HsinChu, Tawain, Province of China ; Department of Electronics Engineering, Feng Chia University, 100 Wenhwa Road, Seatwen, Taichung, Tawain, Province of China ; Department of Electronic Engineering, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Tawain, Province of China ; Department of Electronics Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan, Tao-Yuan, Tawain, Province of China Rights: Copyright 2008 INIST-CNRS ; CC BY 4.0 ; Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS Notes: Electronics

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Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory