Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution
In: A Future of Integrated Electronics: Moving Off the Roadmap, Jg. 96 (2008), Heft 2, S. 343-365
Online
academicJournal
- print, 143 ref
Zugriff:
Well-designed circuits are one key insulating layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to hide more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.
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Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution
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Autor/in / Beteiligte Person: | CALHOUN, Benton H ; YU, CAO ; XIN, LI ; KEN, MAI ; PILEGGI, Lawrence T ; RUTENBAR, Rob A ; SHEPARD, Kenneth L |
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Zeitschrift: | A Future of Integrated Electronics: Moving Off the Roadmap, Jg. 96 (2008), Heft 2, S. 343-365 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2008 |
Medientyp: | academicJournal |
Umfang: | print, 143 ref |
ISSN: | 0018-9219 (print) |
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