A PLL-based synthesizer for tunable digital clock generation in a continuous-time ZA A/D converter
In: AMF/RF[AMS/RF] CMOS Circuit Design for Wireless Transceivers, Jg. 42 (2009), Heft 1, S. 24-33
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Zugriff:
In this paper, the design and implementation of a tunable clock synthesizer for driving two continuous-time ΣΔ ADCs has been carried out. A PLL-based solution, whose phase noise requirements are obtained from system level simulations, was implemented in a 0.35 μm CMOS technology. The frequency of the clock ranges from 12 to 256MHz with a minimum tuning step of 10kHz. The PLL phase noise is kept below -80 dBc/Hz at 1 MHz offset for the entire output range, while drawing 2.2-5.6 mA from a 3.3 V supply voltage.
Titel: |
A PLL-based synthesizer for tunable digital clock generation in a continuous-time ZA A/D converter
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Autor/in / Beteiligte Person: | SEGUNDO, Jokin ; QUINTANILLA, Luis ; ARIAS, Jesus ; ENRIQUEZ, Lourdes ; HERNANDEZ, Jesus M ; VICENTE, José |
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Zeitschrift: | AMF/RF[AMS/RF] CMOS Circuit Design for Wireless Transceivers, Jg. 42 (2009), Heft 1, S. 24-33 |
Veröffentlichung: | Amsterdam: Elsevier, 2009 |
Medientyp: | academicJournal |
Umfang: | print, 25 ref |
ISSN: | 0167-9260 (print) |
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