Low-power, high-gain and low-noise CMOS distributed amplifier for UWB systems
In: Electronics letters, Jg. 45 (2009), Heft 12, S. 634-636
academicJournal
- print, 7 ref
Zugriff:
A 3―10 GHz CMOS distributed amplifier (DA) with flat and low noise figure (NF) and flat and high power gain (S21) is demonstrated. A flat and low NF was achieved by adopting an RL terminating network for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF frequency response. Besides, an flat and high S21 was achieved by using the proposed cascade gain cell, which constitutes a cascode-stage with a low-Q RLC load and an inductive-peaking common-source stage. In the high-gain mode, the DA consumed 37.8 mW and achieved a flat and high S21 of 20.47 ± 0.72 dB with an average NF of 3.29 dB over the 3―10 GHz band of interest, one of the best reported NF performances for a CMOS UWB DA or low-noise amplifier. In the low-gain mode, the DA achieved S21 of 11.03 ± 0.98 dB and an average NF of 4.25 dB with a power dissipation (PD) of 6.86 mW, the lowest PD ever reported for a CMOS UWB DA or LNA with an average S21 of greater than 10 dB.
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Low-power, high-gain and low-noise CMOS distributed amplifier for UWB systems
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Autor/in / Beteiligte Person: | CHANG, J.-F ; LIN, Y.-S |
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Zeitschrift: | Electronics letters, Jg. 45 (2009), Heft 12, S. 634-636 |
Veröffentlichung: | Stevenage: Institution of Engineering and Technology, 2009 |
Medientyp: | academicJournal |
Umfang: | print, 7 ref |
ISSN: | 0013-5194 (print) |
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