An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB THD
In: SPECIAL ISSUE ON THE 2008 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, Jg. 44 (2009), Heft 8, S. 2202-2211
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academicJournal
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Zugriff:
A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. Realized in a 0.18 μm CMOS technology, it provides 81 dB SNDR, 82 dB dynamic range, and -98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 V power supply (analog power 4.4 mW, digital power 3.7 mW). Its figure-of-merit is 0.25 pJ/conversion-step, which is among the best reported for discrete-time delta-sigma ADCs in wideband applications.
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An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB THD
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Autor/in / Beteiligte Person: | LEE, Kyehyung ; MILLER, Matthew R ; TEMES, Gabor C |
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Zeitschrift: | SPECIAL ISSUE ON THE 2008 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, Jg. 44 (2009), Heft 8, S. 2202-2211 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2009 |
Medientyp: | academicJournal |
Umfang: | print, 18 ref |
ISSN: | 0018-9200 (print) |
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