Design procedure for two-stage CMOS opamp with optimum balancing of speed, power and noise

This article presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to establish optimised balancing between speed, power and noise for a given load condition. The proposed design steps allow opamp designers to optimise the power consumption for the given constraints of settling time, accuracy, noise and load. The key factor is to establish the optimum combination of ratios of transconductance of second stage to first stage and load capacitor to compensation capacitor. So, required accuracy and settling time can be established with minimum power consumption. Unlike the earlier reported design procedures, in this article a systematic method is presented to set the quiescent voltages at the transistors of the first and second stages of the opamp. This work will be helpful to select appropriate method of implementation of Miller compensation for given constraints. To verify the viability of the proposed design steps, SPICE simulation results for the proposed procedure are given. Best simulation results obtained on Tanner tool show settling time and power dissipation equal to 320 ns and 188.5 μW, respectively, for 5 pf capacitive load.