Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators : Analog Circuits and Related SoC Integration Technologies
In: IEICE transactions on electronics, Jg. 93 (2010), Heft 6, S. 777-784
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Zugriff:
In this paper we present a study on the design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by the quality factor of inductors. It has been experimentally shown that higher-Q inductors can be achieved at higher frequencies while the oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor size and the degradation of the quality factor caused by a switched-capacitor array are analytically estimated, and the maximum oscillation frequency of VCOs is also derived from an equivalent circuit by considering parasitic capacitances. According to the analytical evaluation, the phase noise of a VCO using a 65 nm CMOS is 2 dB better than that of a 180 nm CMOS.
Titel: |
Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators : Analog Circuits and Related SoC Integration Technologies
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Autor/in / Beteiligte Person: | MURAKAMI, Rui ; HARA, Shoichi ; OKADA, Kenichi ; MATSUZAWA, Akira |
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Zeitschrift: | IEICE transactions on electronics, Jg. 93 (2010), Heft 6, S. 777-784 |
Veröffentlichung: | Oxford: Oxford University Press, 2010 |
Medientyp: | academicJournal |
Umfang: | print, 9 ref |
ISSN: | 0916-8524 (print) |
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