An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology : Analog Circuits and Related SoC Integration Technologies
In: IEICE transactions on electronics, Jg. 93 (2010), Heft 6, S. 820-826
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Zugriff:
An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.
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An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology : Analog Circuits and Related SoC Integration Technologies
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Autor/in / Beteiligte Person: | MATSUNO, Tetsuro ; FUJIMOTO, Daisuke ; KOSAKA, Daisuke ; HAMANISHI, Naoyuki ; TANABE, Ken ; SHIOCHI, Masazumi ; NAGATA, Makoto |
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Zeitschrift: | IEICE transactions on electronics, Jg. 93 (2010), Heft 6, S. 820-826 |
Veröffentlichung: | Oxford: Oxford University Press, 2010 |
Medientyp: | academicJournal |
Umfang: | print, 10 ref |
ISSN: | 0916-8524 (print) |
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