Self-Enabled Error-Free Switching Circuit for Spin Transfer Torque MRAM and Logic
In: IEEE transactions on magnetics, Jg. 48 (2012), Heft 9, S. 2403-2406
Online
academicJournal
- print, 29 ref
Zugriff:
Spin transfer torque (STT) is one of the most promising switching approaches for magnetic tunnel junction (MTJ) nanopillars to build up innovative nonvolatile memory and logic circuits. It presents low critical current (e.g., < 100 μA at 65 nm), simple switching scheme, and fast-speed; however, it suffers from a number of reliability issues like stochastic switching effects, process voltage temperature (PVT) variations, and erroneous reading etc. The mainstream solution is to enlarge the write pulse duration to reduce error rate, which sacrifices the speed and low power advantages. In this paper, we present a new switching circuit for STT memory and logic, allowing error-free as the switching operation becomes deterministic benefiting from the self-enabled mechanism. The switching power efficiency can be also improved thanks to a shorter switching duration. By using an accuracy spice model of STT-MTJ and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its high-reliable write/read operations and evaluate its potential area, power, and speed performance.
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Self-Enabled Error-Free Switching Circuit for Spin Transfer Torque MRAM and Logic
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Autor/in / Beteiligte Person: | LAKYS, Yahya ; WEI SHENG, ZHAO ; DEVOLDER, Thibaut ; YUE, ZHANG ; KLEIN, Jacques-Olivier ; RAVELOSONA, Dafiné ; CHAPPERT, Claude |
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Zeitschrift: | IEEE transactions on magnetics, Jg. 48 (2012), Heft 9, S. 2403-2406 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2012 |
Medientyp: | academicJournal |
Umfang: | print, 29 ref |
ISSN: | 0018-9464 (print) |
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