Ultra-Low-Power Cascaded CMOS LNA With Positive Feedback and Bias Optimization
In: IEEE transactions on microwave theory and techniques, Jg. 61 (2013), Heft 5, S. 1934-1945
Online
academicJournal
- print, 27 ref 1
Zugriff:
A novel circuit topology for a CMOS low-noise amplifier (LNA) is presented in this paper. By employing a positive feedback technique at the common-source transistor of the cascade stage, the voltage gain can be enhanced. In addition, with the MOS transistors biased in the moderate inversion region, the proposed LNA circuit is well suited to operate at reduced power consumption and supply voltage conditions. Utilizing a standard 0.18-μm CMOS process, the CMOS LNA has been demonstrated for 5-GHz frequency band applications. Operated at a supply voltage of 0.6 V, the LNA with the gain-boosting technique achieves a gain of 13.92 dB and a noise figure of 3.32 dB while consuming a dc power of 834 μW. The measured P1-dB and input third-order intercept point are ―22.2 and ―11.5 dBm, respectively.
Titel: |
Ultra-Low-Power Cascaded CMOS LNA With Positive Feedback and Bias Optimization
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Autor/in / Beteiligte Person: | LAI, Mu-Tsung ; TSAO, Hen-Wai |
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Zeitschrift: | IEEE transactions on microwave theory and techniques, Jg. 61 (2013), Heft 5, S. 1934-1945 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2013 |
Medientyp: | academicJournal |
Umfang: | print, 27 ref 1 |
ISSN: | 0018-9480 (print) |
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