Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width
In: Selected extended papers from ULIS 2012 conference, Jg. 88 (2013), S. 32-36
academicJournal
- print, 16 ref
Zugriff:
In this paper, TriGate nanowire (TGNW) FETs with high-κ/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performance of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (subthreshold slope and drain-induced-barrier-lowering) of scaled down TGNW FET is clearly demonstrated.
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Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width
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Autor/in / Beteiligte Person: | COQUAND, R ; BARRAUD, S ; TABONE, C ; BARNOLA, S ; MUNTEANU, D ; GHIBAUDO, G ; MONFRAY, S ; BOEUF, F ; POIROUX, T ; CASSE, M ; LEROUX, P ; VIZIOZ, C ; COMBOROURE, C ; PERREAU, P ; ERNST, E ; SAMSON, M.-P ; MAFFINI-ALVARO, V |
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Zeitschrift: | Selected extended papers from ULIS 2012 conference, Jg. 88 (2013), S. 32-36 |
Veröffentlichung: | Kidlington: Elsevier, 2013 |
Medientyp: | academicJournal |
Umfang: | print, 16 ref |
ISSN: | 0038-1101 (print) |
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