Low Power Magnetic Full-Adder Based on Spin Transfer Torque MRAM
In: IEEE transactions on magnetics, Jg. 49 (2013), Heft 9, S. 4982-4987
Online
academicJournal
- print, 32 ref
Zugriff:
Power issues have become a major problem of CMOS logic circuits as technology node shrinks below 90 nm. In order to overcome this limitation, emerging logic-in-memory architecture based on nonvolatile memories (NVMs) are being investigated. Spin transfer torque (STT) magnetic random access memory (MRAM) is considered one of the most promising NVMs thanks to its high speed, low power, good endurance, and 3-D back-end integration. This paper presents a novel magnetic full-adder (MFA) design based on perpendicular magnetic anisotropy (PMA) STT-MRAM. It provides advantageous power efficiency and die area compared with conventional CMOS-only full adder (FA). Transient simulations have been performed to validate this design by using an industrial CMOS 40 nm design kit and an accurate STT-MRAM compact model including physical models and experimental measurements.
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Low Power Magnetic Full-Adder Based on Spin Transfer Torque MRAM
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Autor/in / Beteiligte Person: | ERYA, DENG ; YUE, ZHANG ; KLEIN, Jacques-Olivier ; RAVELSONA, Dafiné ; CHAPPERT, Claude ; WEISHENG, ZHAO |
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Zeitschrift: | IEEE transactions on magnetics, Jg. 49 (2013), Heft 9, S. 4982-4987 |
Veröffentlichung: | New York, NY: Institute of Electrical and Electronics Engineers, 2013 |
Medientyp: | academicJournal |
Umfang: | print, 32 ref |
ISSN: | 0018-9464 (print) |
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