6.8 mW 15 dBm IIP3 CMOS common-gate LNA employing post-linearisation technique
In: Electronics letters, Jg. 50 (2014), Heft 3, S. 149-151
Online
academicJournal
- print, 7 ref
Zugriff:
A linearised differential common-gate CMOS low-noise amplifier (LNA) is proposed. The linearity is improved by a cross-coupled post-distortion technique, employing PMOS in a weak inversion region as an auxiliary field effect transistor to cancel the third-order nonlinear currents of a common-gate LNA and impair the related second-order nonlinear currents. Meanwhile, the resulting noise figure is little affected. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and gain have about 8.2 and 1.5 dB improvements in the designed frequency band, respectively. A NF of 3.4 dB is obtained with a power dissipation of 6.8 mW under a 1.8 V power supply.
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6.8 mW 15 dBm IIP3 CMOS common-gate LNA employing post-linearisation technique
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Autor/in / Beteiligte Person: | BENQING, GUO ; GUANGJUN, WEN ; SHIQUAN, AN |
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Zeitschrift: | Electronics letters, Jg. 50 (2014), Heft 3, S. 149-151 |
Veröffentlichung: | Stevenage: Institution of Engineering and Technology, 2014 |
Medientyp: | academicJournal |
Umfang: | print, 7 ref |
ISSN: | 0013-5194 (print) |
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