A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core
In: IEEE Access, Jg. 9 (2021), S. 99039-99049
Online
academicJournal
Zugriff:
This paper proposes a simultaneous output power- and gain-matching technique in a sub-THz power amplifier (PA) design based on a maximum achievable gain ( $G_{max}$ ) core. The optimum combination of three-passive-elements-based embedding networks for implementing the $G_{max}$ -core is chosen considering the small- and large-signal performances at the same time. By adopting the proposed technique, the simultaneous output power- and gain-matching can be achieved, maximizing the small-signal power gain and large-signal output power simultaneously. A 150 GHz single-ended two-stage PA without power combining circuit is implemented in a 65-nm CMOS process based on the proposed technique. The amplifier achieves a peak power gain of 17.5 dB, peak power added efficiency (PAE) of 13.3 and 16.1 %, saturated output power ( $P_{sat}$ ) of 10.3 and 9.4 dBm, and DC power consumption of 86.3 and 52.4 mW, respectively, under the bias voltage of 1.2 and 1 V, which corresponds to the highest PAE, gain per stage and $P_{out}$ per single transistor among other reported CMOS D-band PAs.
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A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core
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Autor/in / Beteiligte Person: | Park, Dae-Woong ; Dzuhri Radityo Utomo ; Yun, Byeonghun ; Hafiz Usman Mahmood ; Lee, Sang-Gug |
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Zeitschrift: | IEEE Access, Jg. 9 (2021), S. 99039-99049 |
Veröffentlichung: | IEEE, 2021 |
Medientyp: | academicJournal |
ISSN: | 2169-3536 (print) |
DOI: | 10.1109/ACCESS.2021.3096423 |
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