Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel
In: Sensors, Jg. 12 (2012), Heft 8, S. 10067-10085
Online
academicJournal
Zugriff:
Modern “smart” CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage “smart” image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.
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Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel
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Autor/in / Beteiligte Person: | Yadid-Pecht, Orly ; Fish, Alexander ; Belenky, Alexander ; Teman, Adam ; Spivak, Arthur |
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Zeitschrift: | Sensors, Jg. 12 (2012), Heft 8, S. 10067-10085 |
Veröffentlichung: | MDPI AG, 2012 |
Medientyp: | academicJournal |
ISSN: | 1424-8220 (print) |
DOI: | 10.3390/s120810067 |
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