Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology
In: EPJ Web of Conferences, Jg. 170 (2018), S. 01021-1021
Online
academicJournal
Zugriff:
This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.
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Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology
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Autor/in / Beteiligte Person: | Jeffrey, Prinzie ; Jorgen, Christiansen ; Paulo, Moreira ; Michiel, Steyaert ; Paul, Leroux |
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Zeitschrift: | EPJ Web of Conferences, Jg. 170 (2018), S. 01021-1021 |
Veröffentlichung: | EDP Sciences, 2018 |
Medientyp: | academicJournal |
ISSN: | 2100-014X (print) |
DOI: | 10.1051/epjconf/201817001021 |
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