Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors
In: IEEE Journal of the Electron Devices Society, Jg. 11 (2023), S. 84-94
Online
academicJournal
Zugriff:
The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- $\mu \text{m}$ CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.
Titel: |
Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors
|
---|---|
Autor/in / Beteiligte Person: | Huang, Yi-Chun ; Ker, Ming-Dou |
Link: | |
Zeitschrift: | IEEE Journal of the Electron Devices Society, Jg. 11 (2023), S. 84-94 |
Veröffentlichung: | IEEE, 2023 |
Medientyp: | academicJournal |
ISSN: | 2168-6734 (print) |
DOI: | 10.1109/JEDS.2022.3228859 |
Schlagwort: |
|
Sonstiges: |
|