Extraction of circuit parameters using multi-objective genetic algorithm for design of non-linearly compensated operational amplifiers

In this paper, a CMOS operational amplifier (op-amp) for applications requiring a bandwidth several hundreds of MHz will be designed and optimized. The op-amp is two-stage and compensated by current buffer and a Miller capacitor. In order to reduce the occupied silicon area, the compensation capacitor has been replaced with a capacitance transistor (MOSCAP). The most important issue in designing compensation networks for amplifiers and particularly operational amplifiers is the calculation and selection of the optimal size for the circuit elements. After selecting op-amps designated by the user, the size of the circuit elements including transistors of the op-amps, along with the size of MOSCAPs, is determined by optimization algorithm, and the bandwidth, DC gain, power consumption and chip area will be optimized with this algorithm. Using the proposed technique, analytical relationship from the optimized solutions can be obtained. The obtained relationship indicates what is the best trade-off between phase margin, power and unity gain bandwidth which helps to achieve the desirable properties .A two-stage amplifier based on CBMC techniques has been designed by a commercial 0.18-µm CMOS process. When driving a 1-pF capacitive load, the CBMC amplifier acheives over 70-dB dc gain, 680-MHz gain-bandwidth product (GBW), 65o phase margin, and 350-V/µs average slew rate, while it consumes only 900-µW at a 1.8-V supply. Nearly 34% improvement in bandwidth is obtained while the compensation capacitor size can be reduced to 1/3 of its original size.