An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA
In: International Conference on Emerging Technologies in Electronics, Computing and Communication (ICETECC); (2022-12-07) S. 1-6
Konferenz
Zugriff:
Titel: |
An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA
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Autor/in / Beteiligte Person: | Pathan, Aneela ; Chandio, Adil Hussain ; Aziz, Rizwan |
Quelle: | International Conference on Emerging Technologies in Electronics, Computing and Communication (ICETECC); (2022-12-07) S. 1-6 |
Veröffentlichung: | 2022 |
Medientyp: | Konferenz |
ISBN: | 978-1-6654-9087-0 (print) |
DOI: | 10.1109/ICETECC56662.2022.10069099 |
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