Design of Low Power Pass Transistor Logic Based Adders for Multiplier in 90nm CMOS Process
In: 4th International Conference on Signal Processing and Communication (ICSPC); (2023-03-23) S. 206-210
Konferenz
Zugriff:
Titel: |
Design of Low Power Pass Transistor Logic Based Adders for Multiplier in 90nm CMOS Process
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Autor/in / Beteiligte Person: | R, Durai Balaji ; Shylu Sam, D.S. ; G, Manoj ; Jayanthi, D. ; J, Samson Immanuel ; Babafakruddin, Shaik ; V, Shriashwinraja E G |
Quelle: | 4th International Conference on Signal Processing and Communication (ICSPC); (2023-03-23) S. 206-210 |
Veröffentlichung: | 2023 |
Medientyp: | Konferenz |
ISBN: | 979-8-3503-0077-2 (print) |
DOI: | 10.1109/ICSPC57692.2023.10125717 |
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