Design and Verification of an Adder-Subtractor Using UVM Methodology
In: IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT); (2023-04-08) S. 26-30
Konferenz
Zugriff:
Titel: |
Design and Verification of an Adder-Subtractor Using UVM Methodology
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Autor/in / Beteiligte Person: | Dharani, M. ; Bharathi, M. ; Rajeswari, B.M. ; Yadav, A. Mamatha ; Niranjan, D. ; Reddy, A. Chandra Dheeraj |
Quelle: | IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT); (2023-04-08) S. 26-30 |
Veröffentlichung: | 2023 |
Medientyp: | Konferenz |
ISBN: | 978-1-6654-6261-7 (print) ; 978-1-6654-6260-0 (print) |
ISSN: | 2473-5655 (print) |
DOI: | 10.1109/CSNT57126.2023.10134642 |
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