Floorplanning and Comparative Analysis of 16-bit Synchronous Up/Down Counter in Different CMOS Technology
In: International Conference on Computational Intelligence and Sustainable Engineering Solutions (CISES); (2023-04-28) S. 867-871
Konferenz
Zugriff:
Titel: |
Floorplanning and Comparative Analysis of 16-bit Synchronous Up/Down Counter in Different CMOS Technology
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Autor/in / Beteiligte Person: | Rakesh ; Shah, Owais Ahmad ; Vats, Satvik |
Quelle: | International Conference on Computational Intelligence and Sustainable Engineering Solutions (CISES); (2023-04-28) S. 867-871 |
Veröffentlichung: | 2023 |
Medientyp: | Konferenz |
ISBN: | 979-8-3503-2391-7 (print) |
DOI: | 10.1109/CISES58720.2023.10183608 |
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