A Single-Controller-Four-Output Digital LDO With Priority-Time-Multiplexing Scheme and Clamping Loops in 65-nm CMOS
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Jg. 71 (2024-03-01), Heft 3, S. 1486-1490
Online
academicJournal
Zugriff:
Titel: |
A Single-Controller-Four-Output Digital LDO With Priority-Time-Multiplexing Scheme and Clamping Loops in 65-nm CMOS
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Autor/in / Beteiligte Person: | Chen, F. ; Lu, Y. ; Mok, P.K.T. |
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Zeitschrift: | IEEE Transactions on Circuits and Systems II: Express Briefs, Jg. 71 (2024-03-01), Heft 3, S. 1486-1490 |
Veröffentlichung: | 2024 |
Medientyp: | academicJournal |
ISSN: | 1549-7747 (print) ; 1558-3791 (print) |
DOI: | 10.1109/TCSII.2023.3318583 |
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