High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding With Reconfigurable Pipelined Sorter and SCF-Decoding With Non-Uniform 4-Segment CRC
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Jg. 71 (2024-04-01), Heft 4, S. 2349-2353
Online
academicJournal
Zugriff:
Titel: |
High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding With Reconfigurable Pipelined Sorter and SCF-Decoding With Non-Uniform 4-Segment CRC
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Autor/in / Beteiligte Person: | Shih, X. ; Lee, Y. ; Li, G. ; Xie, J. |
Link: | |
Zeitschrift: | IEEE Transactions on Circuits and Systems II: Express Briefs, Jg. 71 (2024-04-01), Heft 4, S. 2349-2353 |
Veröffentlichung: | 2024 |
Medientyp: | academicJournal |
ISSN: | 1549-7747 (print) ; 1558-3791 (print) |
DOI: | 10.1109/TCSII.2023.3340652 |
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