A Speed Up Method towards DDR Subsystem Functional Verification in SoC
In: IEEE 15th International Conference on ASIC (ASICON); (2023-10-24) S. 1-4
Konferenz
Zugriff:
Titel: |
A Speed Up Method towards DDR Subsystem Functional Verification in SoC
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Autor/in / Beteiligte Person: | Jiang, Yande ; Chen, Na ; Wang, Huiquan ; Zhang, Guangda ; Xia, Jun ; Yan, Xiaobo |
Quelle: | IEEE 15th International Conference on ASIC (ASICON); (2023-10-24) S. 1-4 |
Veröffentlichung: | 2023 |
Medientyp: | Konferenz |
ISBN: | 979-8-3503-1298-0 (print) |
ISSN: | 2162-755X (print) |
DOI: | 10.1109/ASICON58565.2023.10396545 |
Sonstiges: |
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