Design of Full Adder Circuits with Optimized Power and Speed Using CMOS Technique
In: IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS); (2024-02-24) S. 1-5
Konferenz
Zugriff:
Titel: |
Design of Full Adder Circuits with Optimized Power and Speed Using CMOS Technique
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Autor/in / Beteiligte Person: | Rajput, Vishal ; Singh, Abhay Pratap ; Tirkey, Sukeshni ; Nakhate, Sangeeta |
Quelle: | IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS); (2024-02-24) S. 1-5 |
Veröffentlichung: | 2024 |
Medientyp: | Konferenz |
ISBN: | 979-8-3503-4846-0 (print) |
ISSN: | 2688-0288 (print) |
DOI: | 10.1109/SCEECS61402.2024.10482060 |
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