Optimizing FPGA-Based DCN Accelerator with On-Chip Dataflow Reordering and Serial-Parallel Computing Array
In: International Conference on High Performance Big Data and Intelligent Systems (HDIS); (2023-12-06) S. 118-123
Konferenz
Zugriff:
Titel: |
Optimizing FPGA-Based DCN Accelerator with On-Chip Dataflow Reordering and Serial-Parallel Computing Array
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Autor/in / Beteiligte Person: | Zhang, Ming ; Xu, Jian ; He, Jinzhong ; Qin, Hong |
Quelle: | International Conference on High Performance Big Data and Intelligent Systems (HDIS); (2023-12-06) S. 118-123 |
Veröffentlichung: | 2023 |
Medientyp: | Konferenz |
ISBN: | 979-8-3503-9416-0 (print) ; 979-8-3503-9415-3 (print) |
DOI: | 10.1109/HDIS60872.2023.10499540 |
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