A Novel Circuit-Level SEU Hardening Technique for High-Speed SiGe HBT Logic Circuits
In: IEEE Transactions on Nuclear Science, Jg. 54 (2007-12-01), Heft 6, S. 2086-2091
Online
academicJournal
Zugriff:
Titel: |
A Novel Circuit-Level SEU Hardening Technique for High-Speed SiGe HBT Logic Circuits
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Autor/in / Beteiligte Person: | Mukherjee, T. S. ; Sutton, A. K. ; Kornegay, K. T. ; Krithivasan, R. ; Cressler, J. D. ; Niu, G. ; Marshall, P. W. |
Link: | |
Zeitschrift: | IEEE Transactions on Nuclear Science, Jg. 54 (2007-12-01), Heft 6, S. 2086-2091 |
Veröffentlichung: | 2007 |
Medientyp: | academicJournal |
ISSN: | 0018-9499 (print) ; 1558-1578 (print) |
DOI: | 10.1109/TNS.2007.908460 |
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