Low-noise fractional-N PLL design with mixed-mode triple-input LC VCO in 65nm CMOS
In: IEEE Radio Frequency Integrated Circuits Symposium (RFIC); (2010-05-01) S. 61-64
Konferenz
Zugriff:
Titel: |
Low-noise fractional-N PLL design with mixed-mode triple-input LC VCO in 65nm CMOS
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Autor/in / Beteiligte Person: | Sun, Yuanfeng ; Yu, Xueyi ; Rhee, Woogeun ; Ko, Sangsoo ; Choo, Wooseung ; Park, Byeong-Ha ; Wang, Zhihua |
Quelle: | IEEE Radio Frequency Integrated Circuits Symposium (RFIC); (2010-05-01) S. 61-64 |
Veröffentlichung: | 2010 |
Medientyp: | Konferenz |
ISBN: | 978-1-4244-6240-7 (print) ; 978-1-4244-6242-1 (print) ; 978-1-4244-6243-8 (print) |
ISSN: | 1529-2517 (print) ; 2375-0995 (print) |
DOI: | 10.1109/RFIC.2010.5477397 |
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