A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation
In: IEEE International Symposium on Circuits and Systems (ISCAS); (2011-05-01) S. 430-433
Konferenz
Zugriff:
Titel: |
A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation
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Autor/in / Beteiligte Person: | Lee, Won-Young ; Kim, Lee-Sup |
Quelle: | IEEE International Symposium on Circuits and Systems (ISCAS); (2011-05-01) S. 430-433 |
Veröffentlichung: | 2011 |
Medientyp: | Konferenz |
ISBN: | 978-1-4244-9472-9 (print) ; 978-1-4244-9473-6 (print) ; 978-1-4244-9474-3 (print) |
ISSN: | 0271-4302 (print) ; 2158-1525 (print) |
DOI: | 10.1109/ISCAS.2011.5937594 |
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