Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic
In: IEEE International Symposium on Circuits and Systems (ISCAS); (2012-05-01) S. 492-495
Konferenz
Zugriff:
Titel: |
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic
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Autor/in / Beteiligte Person: | Ho, Weng-Geng ; Chong, Kwen-Siong ; Lin, Tong ; Gwee, Bah-Hwee ; Chang, Joseph S. |
Quelle: | IEEE International Symposium on Circuits and Systems (ISCAS); (2012-05-01) S. 492-495 |
Veröffentlichung: | 2012 |
Medientyp: | Konferenz |
ISBN: | 978-1-4673-0218-0 (print) ; 978-1-4673-0217-3 (print) ; 978-1-4673-0219-7 (print) |
ISSN: | 0271-4302 (print) ; 2158-1525 (print) |
DOI: | 10.1109/ISCAS.2012.6272073 |
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