A 40-Gb/s low-power wireline transceiver architecture with multi-phase injection-locked clocking scheme
In: IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT); (2012-10-01) S. 1-4
Konferenz
Zugriff:
Titel: |
A 40-Gb/s low-power wireline transceiver architecture with multi-phase injection-locked clocking scheme
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Autor/in / Beteiligte Person: | Gai, Wei-Xin ; Han, Te |
Quelle: | IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT); (2012-10-01) S. 1-4 |
Veröffentlichung: | 2012 |
Medientyp: | Konferenz |
ISBN: | 978-1-4673-2474-8 (print) ; 978-1-4673-2473-1 (print) ; 978-1-4673-2475-5 (print) |
DOI: | 10.1109/ICSICT.2012.6467711 |
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