An efficient hardware architecture for inter-prediction in H.264/AVC encoders
In: IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS); (2014-04-01) S. 294-297
Konferenz
Zugriff:
Titel: |
An efficient hardware architecture for inter-prediction in H.264/AVC encoders
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Autor/in / Beteiligte Person: | Dang, Nam-Khanh ; Tran, Xuan-Tu ; Merirot, Alain |
Quelle: | IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS); (2014-04-01) S. 294-297 |
Veröffentlichung: | 2014 |
Medientyp: | Konferenz |
ISBN: | 978-1-4799-4560-3 (print) ; 978-1-4799-4558-0 (print) |
DOI: | 10.1109/DDECS.2014.6868813 |
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