Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 24 (2016-04-01), Heft 4, S. 1593-1593
Online
academicJournal
Zugriff:
Titel: |
Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique
|
---|---|
Autor/in / Beteiligte Person: | Farkhani, H. ; Peiravi, A. ; Moradi, F. |
Link: | |
Zeitschrift: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 24 (2016-04-01), Heft 4, S. 1593-1593 |
Veröffentlichung: | 2016 |
Medientyp: | academicJournal |
ISSN: | 1063-8210 (print) ; 1557-9999 (print) |
DOI: | 10.1109/TVLSI.2015.2459726 |
Sonstiges: |
|