A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 25 (2017), Heft 1, S. 344-353
Online
academicJournal
Zugriff:
Titel: |
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique
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Autor/in / Beteiligte Person: | Song, J. ; Lee, H. ; Hwang, S. ; Kim, C. |
Link: | |
Zeitschrift: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 25 (2017), Heft 1, S. 344-353 |
Veröffentlichung: | 2017 |
Medientyp: | academicJournal |
ISSN: | 1063-8210 (print) ; 1557-9999 (print) |
DOI: | 10.1109/TVLSI.2016.2580713 |
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