A Charge-Based Architecture for Energy-Efficient Vector-Vector Multiplication in 65nm CMOS
In: IEEE International Symposium on Circuits and Systems (ISCAS); (2018-05-27) S. 1-5
Konferenz
Zugriff:
Titel: |
A Charge-Based Architecture for Energy-Efficient Vector-Vector Multiplication in 65nm CMOS
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Autor/in / Beteiligte Person: | Sanni, Kayode ; Figliolia, Tomas ; Tognetti, Gaspar ; Pouliquen, Philippe ; Andreou, Andreas |
Quelle: | IEEE International Symposium on Circuits and Systems (ISCAS); (2018-05-27) S. 1-5 |
Veröffentlichung: | 2018 |
Medientyp: | Konferenz |
ISBN: | 978-1-5386-4881-0 (print) |
ISSN: | 2379-447X (print) |
DOI: | 10.1109/ISCAS.2018.8351274 |
Sonstiges: |
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