A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction
In: IEEE Solid-State Circuits Letters, Jg. 1 (2018-12-01), Heft 12, S. 237-240
Online
academicJournal
Zugriff:
Titel: |
A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction
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Autor/in / Beteiligte Person: | Pamula, V.R. ; Sun, X. ; Kim, S.M. ; Rahman, F.u. ; Zhang, B. ; Sathe, V.S. |
Link: | |
Zeitschrift: | IEEE Solid-State Circuits Letters, Jg. 1 (2018-12-01), Heft 12, S. 237-240 |
Veröffentlichung: | 2018 |
Medientyp: | academicJournal |
ISSN: | 2573-9603 (print) |
DOI: | 10.1109/LSSC.2019.2896777 |
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