A 138Fsrms-Integrated-Jitter and −249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS
In: Symposium on VLSI Circuits; (2019-06-01) S. 2
Konferenz
Zugriff:
Titel: |
A 138Fsrms-Integrated-Jitter and −249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS
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Autor/in / Beteiligte Person: | Li, Yi-An ; Niknejad, Ali M. |
Quelle: | Symposium on VLSI Circuits; (2019-06-01) S. 2 |
Veröffentlichung: | 2019 |
Medientyp: | Konferenz |
ISBN: | 978-4-86348-720-8 (print) |
ISSN: | 2158-5636 (print) |
DOI: | 10.23919/VLSIC.2019.8777937 |
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