An Efficient Hardware Design for Combined AES and AEGIS
In: Eighth International Conference on Emerging Security Technologies (EST); (2019-07-01) S. 1-6
Konferenz
Zugriff:
Titel: |
An Efficient Hardware Design for Combined AES and AEGIS
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Autor/in / Beteiligte Person: | Sardar, Amit ; Das, Bijoy ; Chowdhury, Dipanwita Roy |
Quelle: | Eighth International Conference on Emerging Security Technologies (EST); (2019-07-01) S. 1-6 |
Veröffentlichung: | 2019 |
Medientyp: | Konferenz |
ISBN: | 978-1-7281-5546-3 (print) |
ISSN: | 2472-7601 (print) |
DOI: | 10.1109/EST.2019.8806225 |
Sonstiges: |
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